| 2. | The vxibus c - size and i , q channels are employed in this module design , and the sampling rate in each channel reaches 500mhz . the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ) . the timing and logic function are fulfilled by fpga . after the disscusion of signal adjusted , the detailed scheme of this module design have been showed . in this design , there is much logic function design , and it is very strict with the hardware language program . so the basic flow of hardware program design and several very important methods of high speed logic function design , which is described by vhdl , are introduced . also , expatiated the inner modules structure of fpga for forepart circuit , the keystone and difficulties of the design . the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system , and it is very important . the timing simulating results of several pivotal modules are depicted . high - speed signal paths are terminated to match the characteristic impedance . the design undergoes integrity analysis and software simulation
在本模块的设计中,有着大量的逻辑设计,对硬件语言程序的编写要求比较高,因此,文中介绍了硬件程序设计的基本流程,以及几种基于vhdl硬件语言设计在高速逻辑设计中非常重要的方法。同时阐述了本模块设计的前端fpga的内部模块结构,设计的重点、难点,并给出了重要模块的时序仿真结果。高速pcb的设计也是目前实现高速数据采集系统的难点和重点,文中详细的阐明了高速pcb设计中的注意点,以及作者在设计本模块时的经验和心得。 |
